Patent Number: 6,298,411

Title: Method and apparatus to share instruction images in a virtual cache

Abstract: A method of accessing information in a cache of a multithreaded system comprises providing a virtual address of an instruction to be accessed by a thread. Upon a cache miss, the physical address of the information is compared with the physical address of an instruction stored in the cache, and if they match, the instruction is accessed from the cache. Alternatively, the cache is searched for an entry having a virtual address which matches the instruction's virtual address, and having some indication of being associated with the accessing thread. Upon finding such an entry, the instruction is accessed from the cache. In addition, the instruction may be accessed from the cache upon finding a cache entry whose virtual address matches the instruction's virtual address, and which either has an address space matching the address space of the thread, or has an indication that the entry matches all address spaces. A translation lookaside buffer (TLB) maps the accessed instruction's virtual address to a physical address upon a miss. The cache entry's virtual address may also mapped to a physical address by the TLB, whose look-up key comprises a virtual address and an address space identifier. A thread indication in a cache entry, corresponding to the accessing thread, is set when a cache miss is detected, where the physical addresses of the accessed instruction and the cache entry match. When this occurs, the instruction is accessed from the cache.

Inventors: Giacalone; Glenn P. (Westford, MA)

Assignee: Compaq Computer Corporation

International Classification: G06F 12/10 (20060101); G06F 012/08 ()

Expiration Date: 10/02/2018