Patent Number: 6,298,416

Title: Method and apparatus for transmitting control signals within a hierarchial cache memory architecture for a data processing system

Abstract: A method and apparatus for transmitting control signals within a hierarchial cache memory architecture of a data processing system is disclosed. The cache memory hierarchy includes multiple levels of cache memories, each level may have a different size and speed. In response to a processor request for information, a control command is sent to the cache memory hierarchy. The control command includes multiple control blocks. Beginning at the lowest possible cache level of the cache memory hierarchy, a determination is made whether or not there is a cache hit at a current level of the cache memory hierarchy. In response to a determination that there is not a cache hit at the current level, an abbreviated control command is sent to an upper cache level of the cache memory hierarchy, after a control block that corresponds to the current level is removed from the control command.

Inventors: Arimilli; Ravi Kumar (Austin, TX), Arimilli; Lakshminarayana Baba (Austin, TX), Fields, Jr.; James Stephen (Austin, TX), Ghai; Sanjeev (Austin, TX), Reddy; Praveen S. (Austin, TX)

Assignee: International Business Machines Corporation

International Classification: G06F 12/08 (20060101); G06F 012/08 ()

Expiration Date: 10/02/2018