Patent Number: 6,298,418

Title: Multiprocessor system and cache coherency control method

Abstract: In a bus or switch coupled system having a plurality of processor modules and a memory module, the memory module is provided with a unit for returning a write completion acknowledgement (WRITE_ACK) to a write requesting processor module. If a processor module PM1 is under execution of write-back of a cache line upon arrival of a cache coherence check (CCC) issued from a processor module with a cache miss of the cache line, an "INVALID" signal is returned to the CCC issued processor module PMO after a write completion acknowledgment from the memory module is confirmed and the cache line is invalidated. After confirming the "INVALID" signals from other processor modules, the CCC issued processor module issues a READ transaction to the memory module to obtain correct latest data reflecting the write-back data of the processor module.

Inventors: Fujiwara; Shisei (Ebina, JP), Shibata; Masabumi (Kawasaki, JP), Nakajima; Atsushi (Hadano, JP), Hamanaka; Naoki (Tokyo, JP), Irie; Naohiko (Kawasaki, JP)

Assignee: Hitachi, Ltd.

International Classification: G06F 12/08 (20060101); G06F 012/08 ()

Expiration Date: 10/02/2018