Patent Number: 6,298,420

Title: Coherent variable length reads from system memory

Abstract: Method and apparatus for processing serial bus read requests in a memorycontroller when the memory controller interfaces to both a pipelined busand a serial bus. According to the method, the read request message isreceived and is split into several atomic transactions. The atomictransactions are issued on the pipelined bus. Data related to the severalatomic transactions is stored in a queue. The requested data is read fromthe queue and placed in a response message on the serial bus.

Inventors: Chittor; Suresh (Hillsboro, OR), Chen; Chih-Cheh (Hillsboro, OR), Tan; Sin Sim (Hillsboro, OR), Spitz; Jonathan Nick (Portland, OR)


International Classification:

Expiration Date: 10/02/2013