Patent Number: 6,298,423

Title: High performance load/store functional unit and data cache

Abstract: A load/store functional unit and a corresponding data cache of a superscalar microprocessor is disclosed. The load/store functional unit includes a plurality of reservation station entries which are accessed in parallel and which are coupled to the data cache in parallel. The load/store functional unit also includes a store buffer circuit having a plurality of store buffer entries. The store buffer entries are organized to provide a first in first out buffer where the outputs from less significant entries of the buffer are provided as inputs to more significant entries of the buffer.

Inventors: Johnson; William M. (Austin, TX), Witt; David B. (Austin, TX), Chinnakonda; Murali (Austin, TX)

Assignee: Advanced Micro Devices, Inc.

International Classification: G06F 9/38 (20060101); G06F 012/02 ()

Expiration Date: 10/02/2018