Patent Number: 6,298,424

Title: Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation

Abstract: A computer system includes one or more microprocessors. The microprocessors assign a priority level to each memory operation as the memory operations are initiated. In one embodiment, the priority levels employed by the microprocessors include a fetch priority level and a prefetch priority level. The fetch priority level is higher priority than the prefetch priority level, and is assigned to memory operations which are the direct result of executing an instruction. The prefetch priority level is assigned to memory operations which are generated according to a prefetch algorithm implemented by the microprocessor. As memory operations are routed through the computer system to main memory and corresponding data transmitted, the elements involved in performing the memory operations are configured to interrupt the transfer of data for the lower priority memory operation in order to perform the data transfer for the higher priority memory operation. While one embodiment of the computer system employs at least a fetch priority and a prefetch priority, the concept of applying priority levels to various memory operations and interrupting data transfers of lower priority memory operations to higher priority memory operations may be extended to other types of memory operations, even if prefetching is not employed within a computer system. For example, speculative memory operations may be prioritized lower than non-speculative memory operations throughout the computer system.

Inventors: Lewchuk; W. Kurt (Austin, TX), McMinn; Brian D. (Buda, TX), Pickett; James K. (Austin, TX)

Assignee: Advanced Micro Devices, Inc.

International Classification: G06F 13/16 (20060101); G06F 13/18 (20060101); G06F 013/18 ()

Expiration Date: 10/02/2018