Patent Number: 6,298,429

Title: Memory address generator capable of row-major and column-major sweeps

Abstract: An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under test. The address generation provides for movement to any adjacent memory cell, in any direction, including north, south, east, west, northeast, northwest, southeast, and southwest. The address of any memory cell, even the address of a non-adjacent memory cell, may be selectively generated by defining a current memory address, choosing one or more modes by which increment-generated, decrement-generated, or combination increment/decrement addresses that define a next memory address are generated, and generating the row address and the column address of the next memory address in accordance with interdependent row carry-out and column carry-out operations.

Inventors: Scott; Anne P. (Fort Collins, CO), Brauch; Jeffery C (Ft Collins, CO), Fleischman; Jay (Fort Collins, CO)

Assignee: Hewlett-Packard Company

International Classification: G11C 8/12 (20060101); G11C 8/00 (20060101); G11C 29/04 (20060101); G11C 29/20 (20060101); G06F 012/06 ()

Expiration Date: 10/02/2018