Patent Number: 6,298,435

Title: Methods and apparatus for exploiting virtual buffers to increase instruction parallelism in a pipelined processor

Abstract: A method and apparatus for increasing instruction level parallelism using a buffer pointer assignment scheme is implemented whereby rename buffers are assigned during dispatch even though the physical rename registers may not yet be available. These virtual rename buffers are assigned by a buffer pointer assignment table. A virtual bit implemented along with each of the physical rename registers is flipped when an instruction corresponding to the entry stored within a particular physical rename register is completed and the result written to the architected register. Thus, at dispatch time, rename registers are assigned as if there were more rename buffers than there existed physical rename registers.

Inventors: Chan; Kin Shing (Austin, TX), Le; Hung Qui (Austin, TX), Nguyen; Dung Quoc (Austin, TX)

Assignee: International Business Machines Corporation

International Classification: G06F 9/38 (20060101); G06F 009/30 ()

Expiration Date: 10/02/2018