Patent Number: 6,298,436

Title: Method and system for performing atomic memory accesses in a processor system

Abstract: A method and system for atomic memory accesses in a processor system, wherein the processor system is able to issue and execute multiple instructions out of order with respect to a particular program order. A first reservation instruction is speculatively issued to an execution unit of the processor system. Upon issuance, instructions queued for the execution unit which occur after the first reservation instruction in the program order are flushed from the execution unit, in response to detecting any previously executed reservation instructions in the execution unit which occur after the first reservation instruction in the program order. The first reservation instruction is speculatively executed by placing a reservation for a particular data address of the first reservation instruction, in response to completion of instructions queued for the execution unit which occur prior to the first reservation instruction in the program order, such that reservation instructions which are speculatively issued and executed in any order are executed in-order with respect to a partnering conditional store instruction.

Inventors: Kahle; James Allan (Austin, TX), Le; Hung Qui (Austin, TX), Thatcher; Larry Edward (Austin, TX), Shippy; David James (Austin, TX)

Assignee: International Business Machines Corporation

International Classification: G06F 9/38 (20060101); G06F 009/305 (); G06F 009/38 (); G06F 009/44 ()

Expiration Date: 10/02/2018