Patent Number: 6,298,452

Title: Hardware test coverage using inter-chip event filtering in multi-chip simulations

Abstract: A simulator simulates and verifies inter-chip functionality in a multi-chip computer system model. The chips within the multi-chip computer system model are characterized by a combination of detailed, low-level hardware models and generalized, high-level hardware emulators. As the simulator executes, inter-chip events are generated which are caused by interactions among and between the hardware models and the hardware emulators. An event processor processes events generated by the simulator, writing events to an event log file. An inter-chip event detector processes the event log file, filtering out inter-chip events caused by the hardware emulators, logging inter-chip events caused by the hardware models. Isolating inter-chip events caused by hardware models helps verification engineers direct the limited number of simulation cycles available during multi-chip verification, thus increasing the confidence level that the multi-chip computer system design is correct.

Inventors: Hill; Eric L. (San Francisco, CA)

Assignee: Hewlett-Packard Company

International Classification: G01R 31/28 (20060101); G01R 31/3183 (20060101); G06F 009/455 (); G06F 017/50 (); G06F 011/00 ()

Expiration Date: 10/02/2018