Patent Number: 6,298,458

Title: System and method for manufacturing test of a physical layer transceiver

Abstract: A system and method for testing the most complex portions of transceiver devices integrated into digital VLSI chips. The testing is performed in a manufacturing environment with minimal external hardware and using a combination of test-specific circuitry and pattern algorithms built into a mixed signal transceiver implementing a test methodology suitable for application and measurement on a digital tester.

Inventors: Cranford, Jr.; Hayden C. (Apex, NC), Gude; Eirik (Burlington, VT), Iadanza; Joseph A. (Hinesburg, VT), Owczarski; Paul A. (Raleigh, NC), Raymond; Jonathan H. (Jericho, VT)

Assignee: International Business Machines Corporation

International Classification: H04L 12/26 (20060101); G01R 31/28 (20060101); H04B 17/00 (20060101); G01R 031/28 (); G01R 031/08 (); G06F 011/00 ()

Expiration Date: 10/02/2018