Patent Number: 6,298,467

Title: Method and system for reducing hysteresis effect in SOI CMOS circuits

Abstract: A method for reducing a hysteresis effect in silicon-on-insulator CMOScircuits includes the steps of providing a circuit having CMOS objects,defining a beta ratio; resizing the CMOS objects based on the beta ratio,determining if the objects are a minimum size based on predetermined sizecriteria, if the objects are larger than the minimum size, defining ascaling factor based on a performance level of the object and resizing theobject based on the scaling factor such that delay variations of theresized circuit are substantially constant. Also, a computer programproduct is provided for reducing the hysteresis effect.

Inventors: Chuang; Ching-Te K. (South Salem, NY), Pelella; Mario M. (Gainesville, FL), Tretz; Christophe R. (Riverdale, NY)


International Classification:

Expiration Date: 10/02/2013