Patent Number: 6,298,471

Title: Interconnect minimization in processor design

Abstract: Methods and apparatus are described for optimizing interconnections betweenbusses and function units and registers. The method includes identifyingeach bus in a plurality of busses and at least one hardware component towhich each bus is assigned for a given operation. At least two busassignments are identified for which different operations occur on thesame hardware component. Hardware components are assigned for differentoperations occurring on the same hardware component to the same bus. Theoptimization process can be efficiently carried out using conventionalalgorithms for solving assignment problems. Use of these assignmentproblem algorithms provides an efficient and reliable way of optimizingthe bus assignments.

Inventors: Schreiber; Robert S. (Palo Alto, CA)

Assignee:

International Classification:

Expiration Date: 10/02/2013