Patent Number: 6,298,473

Title: Apparatus and method for inhibiting pattern distortions to correct pattern data in a semiconductor device

Abstract: A correction target edge extracting part of a layout pattern data correction apparatus extracts a correction target edge from circuit layout patterns. A density calculation region setting part of the apparatus sets density calculation regions around the center of the correction target edge. An area density calculating part calculates an area density of design patterns within the density calculation regions. Given the area density thus calculated, a correction pattern size calculating part calculates the size of a correction pattern to be superposed on the correction target edge. In accordance with the calculated size, a correction pattern generating part generates the correction pattern. A graphic calculating part adds up the correction pattern and design layout patterns to generate corrected layout patterns.

Inventors: Ono; Yusaku (Tokyo, JP), Moriizumi; Koichi (Tokyo, JP)

Assignee: Mitsubishi Denki Kabushiki Kaisha

International Classification: G03F 7/20 (20060101); G03F 1/14 (20060101); G06F 007/60 (); G06F 017/10 (); G03F 009/00 (); G03C 005/00 ()

Expiration Date: 10/02/2018