Patent Number: 6,307,905

Title: Switching noise reduction in a multi-clock domain transceiver

Abstract: A method for reducing system performance degradation caused by switchingnoise in a system which includes a set of subsystems. Each of thesubsystems includes an analog section and a digital section. Each of theanalog sections operates in accordance with a corresponding one of a setof sampling clock signals which are synchronous in frequency. The digitalsections operate in accordance with a receive clock signal. The receiveclock signal is generated such that it is synchronous in frequency withthe sampling clock signals and has a phase offset with respect to one ofthe sampling clock signals. This phase offset is adjusted such that systemperformance degradation due to coupling of switching noise from thedigital sections to the analog sections is substantially minimized.

Inventors: Agazzi; Oscar E. (Irvine, CA)


International Classification:

Expiration Date: 10/23/2013