Patent Number: 6,307,906

Title: Clock and data recovery scheme for multi-channel data communications receivers

Abstract: The multiple-channel clock and data recovery scheme of the present invention derives a single clock signal from multiple mis-matched data streams. The single clock is phased to provide a clocking signal such that the data sampler of the clock and data recovery scheme performs bit center sampling of the data at the bit center average of all channels. The phase of the recovery clock is the average of all the data stream phases, and is the optimal sampling phase for minimum combined bit error rate of all the channels.

Inventors: Tanji; Todd M. (Egan, MN), Welch; James R. (Maplegrove, MN)

Assignee: Applied Micro Circuits Corporation

International Classification: H03L 7/087 (20060101); H03L 7/099 (20060101); H03L 7/08 (20060101); H03D 13/00 (20060101); H04L 25/14 (20060101); H03L 7/091 (20060101); H03L 7/089 (20060101); H04L 7/033 (20060101); H03D 011/06 ()

Expiration Date: 10/23/2018