Patent Number: 6,307,907

Title: Complex multiplier

Abstract: Complex multiplication is performed using a multiplier by generating time division signals with a first clock and a second clock having a speed twice as fast as the first clock and operating the multiplier in a time division mode by the time division signals. Using a first clock and a second clock, the time division signals delayed by one-forth cycle are generated during one cycle of the first clock. Real element and imaginary element of two complex numbers are stored in D flip flops. A multiplexer driven by the time division signals selects each element of the complex numbers. A multiplier multiplies the selected elements in the selected time order. The multiplication results are latched in a plurality of D flip flops according to the time division signals. The latched multiplication results are added or subtracted with adder and subtracter. The outputs of the adder and subtracter are stored in D flip flops and output from the D flip flops, thereby obtaining the multiplication of two complex numbers. Also, the absolute values of sin .theta. and cos .theta. are stored in memory and subtraction using complements of the number 2 of the absolute values of sin .theta. and cos .theta. reduce the size of the memory by half.

Inventors: Kim; Dae-Hyun (Seoul, KR)

Assignee: Hyundai Electronics, Ind., Co., Ltd.

International Classification: H04L 27/00 (20060101); H04L 023/00 ()

Expiration Date: 10/23/2018