Patent Number: 6,309,800

Title: Process for fabricating semiconductor integrated circuit device, andexposing system and mask inspecting method to be used in the process

Abstract: Herein disclosed is an exposure technology for a semiconductor integratedcircuit device which has a pattern as fine as that of an exposurewavelength. The technology contemplates to improve the resolutioncharacteristics of the pattern by making use of the mutual interference ofexposure luminous fluxes.

Inventors: Okamoto; Yoshihiko (Ohme, JP)


International Classification:

Expiration Date: 10/32013