Patent Number: 6,309,911

Title: Method of fabricating semiconductor device

Abstract: An object of the present invention is to provide a method of fabricating a semiconductor device having a relatively small package structure and hence a relatively small mounting area. An insulating board with a plurality of device carrier areas thereon is prepared, and semiconductor chips are mounted on the respective device carrier areas and then covered with a common resin layer. The resin layer and said insulating board are separated along dicing lines into segments including the device carrier areas thereby to produce individual semiconductor devices. External electrodes connected to electrodes of the semiconductor chips are mounted on the back of the insulating board. The external electrodes are positioned symmetrically with respect to central lines of the packaged semiconductor device for preventing various problems which would otherwise be caused when such a small package is mounted.

Inventors: Hyoudo; Haruo (Gunma, JP), Tani; Takayuki (Gunma, JP), Shibuya; Takao (Gunma, JP)

Assignee: Sanyo Electric Co., Ltd.

International Classification: H01L 23/28 (20060101); H01L 21/02 (20060101); H01L 21/56 (20060101); H01L 23/31 (20060101); H01L 021/44 (); H01L 021/48 (); H01L 024/50 ()

Expiration Date: 10/30/2018