Patent Number: 6,309,912

Title: Method of interconnecting an embedded integrated circuit

Abstract: A method of interconnecting electrical terminations (12) of an integrated circuit die (30) to corresponding circuit traces (22) of a circuit carrying substrate (20). The die is placed in a cavity (24) in the substrate such that the electrical terminations on the die are aligned with corresponding circuit traces on the substrate, and so that the surfaces of the die and substrate are coplanar. A film (40) is vacuum laminated over the substrate and the die with heat and pressure. The film is then heated so that it flows to fill the spaces (34) between the die and sidewalls of the cavity, and is then cured. Excess film is then removed everywhere except that which is in the space between the die and the cavity walls. Electrical interconnections (100) are then plated up between the terminations and the circuit traces to bridge the distance between the terminations and the circuit traces. These interconnections are plated directly on the surface of those portions of the laminated film that lie between the sides of the die and of the cavity.

Inventors: Chiou; Wayne Wen-Haw (Sunrise, FL), Weisman; Douglas H. (Sunrise, FL), Cornett; Kenneth D. (Coral Springs, FL)

Assignee: Motorola, Inc.

International Classification: H01L 21/60 (20060101); H01L 21/52 (20060101); H01L 23/52 (20060101); H01L 21/02 (20060101); H01L 23/12 (20060101); H01L 21/58 (20060101); H01L 23/13 (20060101); H01L 23/538 (20060101); H01L 021/44 ()

Expiration Date: 10/30/2018