Patent Number: 6,309,918

Title: Manufacturable GaAs VFET process

Abstract: A manufacturable GaAs VFET process includes providing a doped GaAs substrate with a lightly doped first epitaxial layer thereon and a heavily doped second epitaxial layer positioned on the first epitaxial layer. A temperature tolerant conductive layer is positioned on the second epitaxial layer and patterned to define a plurality of elongated, spaced apart source areas. Using the patterned conductive layer, a plurality of gate trenches are etched into the first epitaxial layer adjacent the source areas. The bottoms of the gate trenches are implanted and activated to form gate areas. A gate contact is deposited in communication with the implanted gate areas, a source contact is deposited in communication with the patterned conductive layer overlying the source areas, and a drain contact is deposited on the rear surface of the substrate.

Inventors: Huang; Jenn-Hwa (Gilbert, AZ), Gable; Benjamin W. (Chandler, AZ), Eisenbeiser; Kurt (Tempe, AZ), Rhine; David (Phoenix, AZ)

Assignee: Motorola, Inc.

International Classification: H01L 21/02 (20060101); H01L 29/66 (20060101); H01L 21/338 (20060101); H01L 29/812 (20060101); H01L 021/338 ()

Expiration Date: 10/30/2018