Patent Number: 6,309,919

Title: Method for fabricating a trench-gated vertical CMOS device

Abstract: Complementary metal-oxide-semiconductor (CMOS) transistors (18,22) are formed with vertical channel regions (30,52) on an insulator substrate (14). Highly doped polysilicon gates (44,68) are formed in trenches (36,58) to extend laterally around the channel regions (30,52) as insulatively displaced therefrom by gate insulators (41,62) that are grown on the sidewalls of the trenches (36,58). The transistors (18,22), which are formed in respective mesas (20,24) have deeply implanted source regions (28,50) that are ohmically connected to the semiconductor surface via respective source connector regions (34,70).

Inventors: Liu; Yowjuang W. (San Jose, CA), Wollesen; Donald L. (Saratoga, CA)

Assignee: Advanced Micro Devices, Inc.

International Classification: H01L 21/70 (20060101); H01L 29/66 (20060101); H01L 27/12 (20060101); H01L 29/786 (20060101); H01L 21/84 (20060101); H01L 29/78 (20060101); H01L 021/823 ()

Expiration Date: 10/30/2018