Patent Number: 6,309,921

Title: Semiconductor device and method for fabricating semiconductor device

Abstract: The semiconductor device comprises a semiconductor substrate 10 of a first conduction-type, first wells 20a, 20b of a second conduction-type formed in a first region on the primary surface of the semiconductor substrate 10, a second well 22a formed in a second region on the primary surface of the semiconductor substrate 10 other than the first region, a third well 22b of the first conduction-type formed in the first well, and high-concentration impurity-doped layers 26 of the first conduction-type formed in deep portions of the semiconductor substrate spaced from the primary surface of the semiconductor device in device regions. In the semiconductor device having triple wells according to the present invention, the high-concentration impurity-doped layers are formed in deep portions inside of the device regions. Accordingly, in the case where the wells have a low concentration so that the transistors have a low threshold voltage, the deep portions of the wells can independently have a high concentration. As a result, punch-through between the source/drain diffused layer of the transistor formed in the well in the well (double wells), and the well outside of the double wells can be prevented. This structure is also effective to prevent latch-up.

Inventors: Ema; Taiji (Kawasaki, JP), Itabashi; Kazuo (Kawasaki, JP), Ikemasu; Shinichiroh (Kawasaki, JP), Mitani; Junichi (Kawasaki, JP), Yanagita; Itsuo (Kawasaki, JP), Suzuki; Seiichi (Kawasaki, JP)

Assignee: Fujitsu Limited

International Classification: H01L 27/085 (20060101); H01L 27/092 (20060101); H01L 021/823 ()

Expiration Date: 10/30/2018