Patent Number: 6,309,922

Title: Method for fabrication of on-chip inductors and related structure

Abstract: Method for fabrication of on-chip inductors and related structure are disclosed. According to one embodiment, inductors are formed by patterning conductors within a certain dielectric layer in a semiconductor die. Thereafter, the entire dielectric layer in the semiconductor die is subjected to a blanket implantation or sputtering of high permeability material. According to another embodiment, a first area in a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor die includes a patterned conductor which is to be used as an inductor. The patterned conductor is also covered, for example, with photoresist. The second area, excluding the covered patterned conductor is subjected to implantation or sputtering of high permeability material. According to yet another embodiment, a first area of a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor area includes a patterned conductor which is to be used as an inductor. This second area, including the patterned conductor, is subjected to implantation or sputtering of high permeability material. The implantation or sputtering of high permeability materials result in the inductors having much higher inductance values than they would otherwise have.

Inventors: Liu; Q. Z. (Irvine, CA), Zhao; Bin (Irvine, CA), Howard; David (Irvine, CA)

Assignee: Conexant Systems, Inc.

International Classification: H01L 21/02 (20060101); H01L 27/08 (20060101); H01L 021/823 ()

Expiration Date: 10/30/2018