Patent Number: 6,309,923

Title: Method of forming the capacitor in DRAM

Abstract: A method of forming a capacitor with a self-align structure on a substrate, the substrate including a word line and an active region, the method including the steps of forming a first dielectric layer on the active region and the word line with a planar top surface, creating a contact hole in the first dielectric layer with the self-align structure to expose portions of the active region and the word line, forming a conductive layer on the bottom of the contact hole, forming a polysilicon spacer on the sidewall of the contact hole, forming a dielectric spacer on the sidewall of the polysilicon spacer, filling the contact hole with a polysilicon bar, creating three sub-contact holes by etching back the polysilicon spacer and the polysilicon bar with part of the polysilicon spacer and the polysilicon bar remaining on the bottom, forming a hemispherical grain (HSG) layer on the surface of the sub-contact holes, depositing a second dielectric layer on the hemispherical grain, and forming a top electrode on the second dielectric layer.

Inventors: Tseng; Horng-Huei (Hsinchu, TW)

Assignee: Vanguard International Semiconductor Corporation

International Classification: H01L 21/02 (20060101); H01L 21/70 (20060101); H01L 21/314 (20060101); H01L 21/8242 (20060101); H01L 21/316 (20060101); H01L 021/824 (); H01L 021/20 ()

Expiration Date: 10/30/2018