Patent Number: 6,309,924

Title: Method of forming self-limiting polysilicon LOCOS for DRAM cell

Abstract: A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner is deposited on the silicon trench walls. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer. A layer of amorphous silicon is then deposited over the nitride liner. A silicon nitride layer is deposited on the oxidized surface of the amorphous silicon. A resist is formed in the lower portion of the trench, and the exposed silicon nitride layer on top of the amorphous silicon is removed, leaving the upper portion of the amorphous silicon layer exposed. The upper portion of the layer of amorphous silicon is then oxidized so as to form a relatively thin, uniform collar along the entire circumference of the trench. The nitride liner underlying the amorphous silicon layer enhances the thickness uniformity of the amorphous silicon layer and thereby the uniformity of the resulting oxide collar. The nitride liner also acts to limit lateral oxidation of the silicon trench walls during oxidation of the amorphous silicon layer. The nitride liner underlying the collar is also effective in cell operation to control the cell charge at the collar-substrate interface.

Inventors: Divakaruni; Ramachandra (Somers, NY), Mandelman; Jack Allan (Stormville, NY), McStay; Irene Lennox (Hopewell Junction, NY), Nesbit; Larry A. (Farmington, CT), Radens; Carl John (LaGrangeville, NY), Tews; Helmut Horst (Poughkeepsie, NY)

Assignee: International Business Machines Corporation

International Classification: H01L 21/70 (20060101); H01L 21/8242 (20060101); H01L 021/824 ()

Expiration Date: 10/30/2018