Patent Number: 6,309,927

Title: Method of forming high K tantalum pentoxide Ta2O5 instead of ONO stacked films to increase coupling ratio and improve reliability for flash memory devices

Abstract: In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising an oxide layer over the first polysilicon layer, and a tantalum pentoxide layer over the oxide layer, wherein the tantalum pentoxide layer is made by chemical vapor deposition at a temperature from about 200.degree. C. to about 650.degree. C. using an organic tantalum compound and an oxygen compound, and heating in an N.sub.2 O atmosphere at a temperature from about 700.degree. C. to about 875.degree. C.; forming a second polysilicon layer over the insulating layer; etching at least the first polysilicon layer, the second polysilicon layer and the insulating layer, thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

Inventors: Au; Kenneth Wo-Wai (Fremont, CA), Chang; Kent Kuohua (Cupertino, CA), Chi; David (Sunnyvale, CA)

Assignee: Advanced Micro Devices, Inc.

International Classification: H01L 21/02 (20060101); H01L 21/28 (20060101); H01L 021/824 ()

Expiration Date: 10/30/2018