Patent Number: 6,309,928

Title: Split-gate flash cell

Abstract: A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F--N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.

Inventors: Sung; Hung-Cheng (Hsin-Chu, TW), Kuo; Di-Son (Hsin Chu, TW), Yeh; Chuang-Ke (Hsin Chu, TW), Hsieh; Chia-Ta (Tainan, TW), Lin; Yai-Fen (Taichung, TW), Chu; Wen-Ting (Kaoshiung, TW)

Assignee: Taiwan Semiconductor Manufacturing Company

International Classification: H01L 21/02 (20060101); H01L 29/66 (20060101); H01L 21/336 (20060101); H01L 29/76 (20060101); H01L 29/788 (20060101); H01L 021/336 ()

Expiration Date: 10/30/2018