Patent Number: 6,309,929

Title: Method of forming trench MOS device and termination structure

Abstract: A method for fabricating trench MOS devices and termination structure simultaneously is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on the semiconductor substrate prepared. The method comprises following steps: firstly, forming a plurality of first trenches for forming the trench MOS devices in an active region, and a second trench for forming the termination structure. Thereafter, a thermal oxidation process to form a gate oxide on all areas is performed. Then, the first trenches and the second trench are refilled with a first conductive material. An etching back is carried out to remove excess first conductive material so as to form spacer in the second trench and to fill the first trenches only. Next, the gate oxide layer is removed. For IGBT or DMOS device, an extra thermal oxidation and an etching step are required to form inter-conductive oxide layer whereas for Schottky diode, these two steps are skipped. Thereafter, a termination structure oxide layer is formed through deposition, lithographic process and etching. After backside unnecessary layers removal, a sputtering metal layers deposition, lithographic process and etching step are successively performed to form the first electrode with a desired ended location and the second electrode on both side of semiconductor substrate.

Inventors: Hsu; Chih-Wei (Hsinchu, TW), Liu; Chung-Min (Kaohsiung, TW), Kao; Ming-Che (Tainan, TW), Tsai; Ming-Jinn (Hsinchu, TW), Kung; Pu-Ju (Taipei, TW)

Assignee:

International Classification: H01L 29/02 (20060101); H01L 21/331 (20060101); H01L 21/02 (20060101); H01L 29/78 (20060101); H01L 29/66 (20060101); H01L 29/872 (20060101); H01L 21/336 (20060101); H01L 29/06 (20060101); H01L 29/739 (20060101); H01L 021/336 ()

Expiration Date: 10/30/2018