Patent Number: 6,309,931

Title: Method of making a semiconductor device with sidewall insulating layers inthe capacitor contact hole

Abstract: Source/drain regions of an MOS transistor are formed at a surface of ap-type silicon substrate. A storage node electrically connected to thesource/drain regions penetrates a bit line to reach the n-typesource/drain region. The storage node and the bit line are insulated fromeach other by a sidewall insulating layer. Thus, a semiconductor memorydevice suitable for high integration is obtained in which short-circuitbetween the storage node and the bit line on a gate electrode layer can beprevented.

Inventors: Hachisuka; Atsushi (Hyogo, JP), Noguchi; Takeshi (Hyogo, JP)


International Classification:

Expiration Date: 10/32013