Patent Number: 6,309,937

Title: Method of making shallow junction semiconductor devices

Abstract: Disclosed is a technique to provide an integrated circuit substrate with a transistor gate member that has opposing sidewalls. A first spacer extends from one of the sidewalls and a second spacer extends from another of the sidewalls. A source region and a drain region of the substrate are doped, with the first and second spacers correspondingly masking first and second regions of the substrate. The first and second spacers are removed after doping and the first and second regions are exposed. The exposed first and second regions are then doped. The substrate is heated after this second doping stage to simultaneously activate dopant in the source region, the drain region, the first region, and the second region. A third spacer is then formed on the first region and a fourth spacer is then formed on the second region. A suicide contact is established with at least the transistor member, the source region, or the drain region after formation of the third and fourth spacers.

Inventors: Lin; Xi-Wei (Fremont, CA)

Assignee: VLSI Technology, Inc.

International Classification: H01L 21/70 (20060101); H01L 21/02 (20060101); H01L 21/336 (20060101); H01L 21/8234 (20060101); H01L 021/336 ()

Expiration Date: 10/30/2018