Patent Number: 6,309,940

Title: Latch-up resistant CMOS structure

Abstract: Provided with a semiconductor device including: a semiconductor substratehaving a first conductivity type; a first well having a secondconductivity type formed in a first region in a major surface of thesemiconductor substrate; a second well having the first conductivity typeformed in a second region in the major surface of the semiconductorsubstrate; a first MOS transistor having the first conductivity type and afirst contact region having the second conductivity type formed in thefirst well; a second MOS transistor having the second conductivity typeand a second contact region having the second conductivity type formed inthe second well; a heavily doped region of buried layer having the secondconductivity type formed at a portion corresponding to the first contactregion in the first well; and a heavily doped region of buried layerhaving the first conductivity type formed at a portion corresponding tothe second contact region in the second well.

Inventors: Lee; Joo-Hyong (Chungcheongbuk-do, KR)

Assignee:

International Classification:

Expiration Date: 10/32013