Patent Number: 6,309,941

Title: Methods of forming capacitors

Abstract: The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. The invention also includes a capacitor comprising: a) a first capacitor plate; b) a second capacitor plate; c) a capacitor dielectric layer intermediate the first and second capacitor plates; and d) at least one of the first and second capacitor plates comprising a surface against the capacitor dielectric layer and wherein said surface comprises both doped rugged polysilicon and doped non-rugged polysilicon.

Inventors: Parekh; Kunal R. (Boise, ID), Zahurak; John K. (Boise, ID), Wald; Phillip G. (Boise, ID)

Assignee: Micron Technology, Inc.

International Classification: H01L 21/70 (20060101); H01L 21/02 (20060101); H01L 29/66 (20060101); H01L 21/8242 (20060101); H01L 29/94 (20060101); H01L 021/20 ()

Expiration Date: 10/30/2018