Patent Number: 6,309,942

Title: STI punch-through defects and stress reduction by high temperature oxide reflow process

Abstract: A method of manufacturing a semiconductor device with reduced shallow trench isolation defects and stress is disclosed. The disclosed method begins by providing a silicon substrate including a capping layer. A plurality of isolation trenches are then etched through the capping layer and into the silicon substrate to form a plurality of isolation regions in the silicon substrate. The isolation trenches are then filled with an oxide layer. The oxide layer and the capping layer are then polished back using techniques known in the art. After polishing, the semiconductor device is annealed between a temperature range of about C. to about C.

Inventors: Tsui; Ting Y. (Palo Alto, CA), Tu; Robert H. (Sunnyvale, CA), Li; Xiao-Yu (San Jose, CA), Mehta; Sunil D. (San Jose, CA)

Assignee: Advanced Micro Devices, Inc.

International Classification: H01L 21/70 (20060101); H01L 21/762 (20060101); H01L 021/76 ()

Expiration Date: 10/30/2018