Patent Number: 6,309,946

Title: Reduced RC delay between adjacent substrate wiring lines

Abstract: A void is defined between adjacent wiring lines to minimize RC coupling. The void has a low dielectric value approaching 1.0. For one approach, hollow silicon define the void. The spheres are fabricated to a known inner diameter, wall thickness and outer diameter. The spheres are ridgid enough to withstand the mechanical processes occurring during semiconductor fabrication. The spheres withstand elevated temperature up to a prescribed temperature range. At or above a desired temperature, the sphere walls disintegrate leaving the void in place. For an alternative approach, adjacent wiring lines are "T-topped" (i.e., viewed cross-sectionally). Dielectric fill deposited in the spacing between lines. As the dielectric material accumulates on the line and substrate walls, the T-tops grow toward each other. Eventually, the T-tops meet sealing off and internal void.

Inventors: Givens; John H. (Meridian, ID)

Assignee: Micron Technology, Inc.

International Classification: H01L 21/70 (20060101); H01L 23/532 (20060101); H01L 23/52 (20060101); H01L 23/522 (20060101); H01L 21/768 (20060101); H01L 23/528 (20060101); H01L 21/764 (20060101); H01L 021/76 ()

Expiration Date: 10/30/2018