Patent Number: 6,309,948

Title: Method for fabrication of a semiconductor device

Abstract: A method for forming a semiconductor structure on an active area mesa with minimal loss of field oxide deposited in isolation trenches adjacent the mesa. The trench insulating material is protected by an etch barrier layer having at least a partial resistance to etchants used in further device processing steps. The barrier layer may also be deposited over the surface of the substrate to protect it from damage during device processing. The barrier layer may be removed by an etchant having a selectivity for the barrier layer over that of the surrounding device elements. Final processing of the device may be completed once the barrier layer is removed.

Inventors: Lin; Xi-Wei (Fremont, CA), Lee; Henry (San Francisco, CA), Harvey; Ian R. (Kaysville, UT)

Assignee: VLSI Technology, Inc.

International Classification: H01L 21/02 (20060101); H01L 21/311 (20060101); H01L 021/76 ()

Expiration Date: 10/30/2018