Patent Number: 6,309,949

Title: Semiconductor isolation process to minimize weak oxide problems

Abstract: A process for forming an isolation region while substantially eliminating weak oxide effects, comprising the steps of obtaining a semiconductor substrate patterned with a plurality of mesas with sidewalls, each of the mesas comprising at least a first insulator layer and a second different insulated layer thereover, forming a trench between the mesas into the semiconductor substrate, removing a lateral portion of the first insulator layer exposed at the sidewalls of the mesas to thereby undercut the second insulator layer at its sidewall edges, forming an oxide layer on exposed areas of the semiconductor substrate below the undercut of the second insulator layer, and filling the trench with an insulator material.

Inventors: He; Yue Song (San Jose, CA), Liu; Yowjuang William (San Jose, CA)

Assignee: Advanced Micro Devices, Inc.

International Classification: H01L 21/70 (20060101); H01L 21/762 (20060101); H01L 021/76 (); H01L 021/336 (); H01L 023/58 ()

Expiration Date: 10/30/2018