Patent Number: 6,309,950

Title: Methods for making silicon-on-insulator structures

Abstract: Some advanced integrated circuits are fabricated as silicon-on-insulatorstructures, which facilitate faster operating speeds, closer componentspacing, lower power consumption, and so forth. Unfortunately, currentbonded-wafer techniques for making such structures are costly because theywaste silicon. Accordingly, one embodiment of the invention provides asmart-bond technique that allows repeated use of a silicon wafer toproduce hundreds and potentially thousands of silicon-on-insulatorstructures, not just one or two as do conventional methods. Moreprecisely, the smart bond technique entails bonding selected first andsecond regions of a silicon substrate to an insulative substrate and thenseparating the two substrates to leave silicon protrusions or islands onthe insulative substrate. The technique is also suitable to formingthree-dimensional integrated circuits, that is, circuits having two ormore circuit layers.

Inventors: Forbes; Leonard (Corvallis, OR)

Assignee:

International Classification:

Expiration Date: 10/32013