Patent Number: 6,309,959

Title: Formation of self-aligned passivation for interconnect to minimize electromigration

Abstract: An interconnect opening of an integrated circuit is filled with a conductive fill with the interconnect opening being within an insulating layer on a semiconductor wafer. A seed layer of a first conductive material is deposited conformally onto sidewalls and a bottom wall of the interconnect opening. The interconnect opening is further filled with a second conductive material by growing the second conductive material from the seed layer to form a conductive fill of the first conductive material and the second conductive material within the interconnect opening. The first conductive material and the second conductive material are comprised of a bulk metal, and at least one of the first conductive material and the second conductive material is a metal alloy having an alloy dopant in the bulk metal. In addition, a plasma treatment process is performed to remove any metal oxide or metal hydroxide from a top surface of the conductive fill. A self-aligned passivation material of an intermetallic compound or a metal oxide is formed at the top surface of the conductive fill with the alloy dopant that segregates out and to the top surface of the conductive fill. The intermetallic compound or the metal oxide is an additional passivation material between the top surface of the conductive fill and a layer of bulk passivation material deposited over the semiconductor wafer to prevent drift of the bulk metal, such as copper, of the conductive fill along a bottom surface of the layer of bulk passivation material.

Inventors: Wang; Pin-Chin C. (Menlo Park, CA), You; Lu (Santa Clara, CA), Bernard; Joffre (Santa Clara, CA), Marathe; Amit (Santa Clara, CA)

Assignee: Advanced Micro Devices, Inc.

International Classification: H01L 21/70 (20060101); H01L 21/768 (20060101); H01L 021/476 ()

Expiration Date: 10/30/2018