Patent Number: 6,309,961

Title: Method of forming damascene wiring in a semiconductor device

Abstract: A method of polishing a metal film which is used for forming damascene wirings or conductors by polishing a metal film formed on an insulating film having trenches thereon by using a CMP, in which excess polishing, that is, dishing, of buried conductors having large area occurring when the metal film is polished by the CMP method can be restrained. The method comprises: providing a substrate on which an insulating film is formed; forming a trench in the insulating film; forming a buried metal film portion in the trench whose width is equal to or larger than 1 micrometer; forming a first metal film on the insulating film such that the buried metal film portion is covered by the first metal film; and polishing a surface of the first metal film by using a CMP method. A lower portion of the buried metal film portion is buried in the trench whose width is equal to or larger than 1 micrometer, and at least a part of an upper portion of the buried metal film portion is located higher than the top surface of the insulating film.

Inventors: Kubo; Akira (Tokyo, JP)

Assignee: NEC Corporation

International Classification: H01L 21/70 (20060101); H01L 21/768 (20060101); H01L 021/476 ()

Expiration Date: 10/30/2018