Patent Number: 6,309,968

Title: Method to improve intrinsic refresh time and dichlorosilane formed gate oxide reliability

Abstract: The intrinsic refresh time of a DRAM and the reliability of the gate oxide of the pass transistor of the memory cell of the DRAM is improved by a method to form electronic components of an integrated circuit on a semiconductor substrate that will eliminate damage to molecular bonds and reduce junction leakage within the semiconductor substrate. The method begins by forming said electronic components using recognized methods to create implantations, insulating oxide layers, selectively etching the insulating oxide layers and deposited conductive layers to assemble the transistors and capacitors of the integrated circuit. Interconnections between the electronic components are then formed. The interconnections include multiple layers of metal, multiple layers of heavily doped polycrystalline silicon, and silicon/metal alloys to connect terminals of said electronic components to the multiple layers of metals and multiple layers of heavily doped polycrystalline silicon. The molecular bonds are then repaired by sintering the semiconductor substrate in an atmosphere of atomic hydrogen (H.sub.2) for a time and a temperature sufficient to repair damage to the molecular bonds within said semiconductor substrate so as to reduce said junction leakage of said transistors and to remove traps between the surface of the semiconductor substrate and the gate oxide of the transistors.

Inventors: Chu; Huey-Chi (Taipei, TW), Lin; Yeh-Sen (Tao-Yuan, TW)

Assignee: Vanguard International Semiconductor Corporation

International Classification: H01L 21/30 (20060101); H01L 21/02 (20060101); H01L 21/285 (20060101); H01L 21/28 (20060101); H01L 21/324 (20060101); H01L 021/44 ()

Expiration Date: 10/30/2018