Patent Number: 6,309,969

Title: Copper metallization structure and method of construction

Abstract: The invention is directed to the use of copper as via and interconnect structures for an integrated circuit. The process in accordance with a preferred embodiment produces an interconnect layer of continuous copper with superior adhesion while requiring only a minimum number of steps for its production. This process addresses the current need in semiconductor manufacturing for reliable and performance-oriented vias and interconnect structures, while not being susceptible to many of the problems which plague the use of aluminum for similar structures. Fabrication of an integrated circuit in accordance with a preferred embodiment of the invention begins with the formation of semiconductor devices on a silicon wafer. Next, an intermetallic dielectric layer (IDL) is formed by materials such as silicon dioxide (SiO.sub.2), polymide, or silicon nitride over the devices. This step is followed by the laying of a diffusion barrier layer on the IDL surface. The resulting product is then exposed to an electrochemical deposition or electroplating stage for the formation of a copper layer directly on top of the diffusion barrier layer. In accordance with a preferred embodiment of the invention, a variable voltage is applied to the electrochemical process in two different stages. The first stage produces nucleation of a high density of clusters and the second stage permits diffusion limited growth of the clusters so as to produce a continuous copper film layer.

Inventors: Oskam; Gerko (Baltimore, MD), Searson; Peter C. (Baltimore, MD), Vereecken; Philippe M. (Baltimore, MD), Long; John G. (Baltimore, MD), Hoffmann; Peter M. (Baltimore, MD)

Assignee: The John Hopkins University

International Classification: H01L 21/02 (20060101); H01L 21/288 (20060101); H01L 21/70 (20060101); H01L 21/768 (20060101); H01L 021/44 ()

Expiration Date: 10/30/2018