Patent Number: 6,309,970

Title: Method of forming multi-level copper interconnect with formation of copper oxide on exposed copper surface

Abstract: There is presented a semiconductor device including multiple levels of copper interconnects; wherein the surface of a copper interconnect corresponding to at least one underlying layer of another copper interconnect layer is turned into copper oxide to a thickness of 30 nm or more by oxidation conducted at the oxidation rate of 20 nm/minor less, and thereby the reflection of the exposure light from the lower-level copper interconnect is prevented, in forming by means of photolithography a trench to form a copper interconnect through damascening.

Inventors: Ito; Nobukazu (Tokyo, JP), Matsubara; Yoshihisa (Tokyo, JP)

Assignee: NEC Corporation

International Classification: H01L 23/532 (20060101); H01L 23/52 (20060101); H01L 21/70 (20060101); H01L 21/768 (20060101); H01L 21/02 (20060101); H01L 21/321 (20060101); H01L 021/44 ()

Expiration Date: 10/30/2018