Patent Number: 6,309,980

Title: Semiconductor integrated circuit arrangement fabrication method

Abstract: To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.

Inventors: Tokunaga; Takafumi (Iruma, JP), Okudaira; Sadayuki (Ohme, JP), Mizutani; Tatsumi (Koganei, JP), Tago; Kazutami (Hitachinaka, JP), Kazumi; Hideyuki (Hitachi, JP), Yoshioka; Ken (Kudamatsu, JP)

Assignee: Hitachi, Ltd.

International Classification: H01L 21/02 (20060101); H01L 21/70 (20060101); H01L 21/768 (20060101); H01L 21/311 (20060101); H01L 021/00 ()

Expiration Date: 10/30/2018