Patent Number: 6,310,361

Title: Electrical test structure on a semiconductor substrate and test method

Abstract: The test structure has a row of transistors with at least two transistors. The S/D regions of the transistors are connected in series and the first and the last S/D region in the row can be connected. Possible etching of the gate polysilicon can be ascertained by measuring the resistance between the terminals given a suitable gate potential. The invention enables, in particular, in situ monitoring of a KOH attack on the n-doped gate polysilicon in a DRAM memory cell.

Inventors: Lichter; Gerd (Radeburg, DE)

Assignee: Infineon Technologies AG

International Classification: H01L 21/70 (20060101); H01L 23/544 (20060101); H01L 21/8242 (20060101); H01L 023/58 (); H01L 021/66 ()

Expiration Date: 10/30/2018