Patent Number: 6,310,367

Title: MOS transistor having a tensile-strained SI layer and a compressive-strained SI-GE layer

Abstract: A semiconductor device in which an NMOSFET and a PMOSFET are formed in a silicon substrate, wherein the gate electrodes of NMOSFET and PMOSFET are made of metallic materials, an Si--Ge layer is formed in at least part of the surface regions including the respective channel layers of the NMOSFET and PMOSFET, and the concentration of Ge in the channel layer of the NMOSFET is lower than the concentration of Ge in the channel layer of the PMOSFET.

Inventors: Yagishita; Atsushi (Yokohama, JP), Matsuo; Kouji (Yokohama, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: H01L 29/786 (20060101); H01L 21/8238 (20060101); H01L 31/06 (20060101); H01L 21/70 (20060101); H01L 27/085 (20060101); H01L 29/78 (20060101); H01L 31/109 (20060101); H01L 31/0328 (20060101); H01L 31/102 (20060101); H01L 31/0264 (20060101); H01L 27/092 (20060101); H01L 29/66 (20060101); H01L 31/072 (20060101); H01L 31/0336 (20060101); H01L 031/072 (); H01L 031/109 (); H01L 031/032 (); H01L 031/033 ()

Expiration Date: 10/30/2018