Patent Number: 6,310,384

Title: Low stress semiconductor devices with thermal oxide isolation

Abstract: A width of a circuit device isolation region and a width of a device region formed on a semiconductor substrate are determined in such a manner as to satisfy a condition which prevents the occurrence of dislocation due to thermal oxidation for forming the isolation region. In accordance with the manufacturing scheme, a semiconductor device produced includes a semiconductor substrate, a plurality of circuit regions formed on a device formation region in the semiconductor substrate and having a width of 0.1 to 125 .mu.m and device isolation regions so formed on the semiconductor substrate as to isolate a plurality of circuit regions from one another and having a width of 0.01 to 2.5 .mu.m. In such a schemed device, a ratio of the width of the device region to the width of the device isolation region is from 2 to 50. Each device isolation region is a groove formed in the semiconductor substrate by etching a portion, among the pad oxide film formed on the surface of the semiconductor substrate and a nitride film formed on the pad oxide film, existing on the device isolation region, and having a depth of from 0 to 10 nm when measured from the position of the pad oxide film on the semiconductor substrate.

Inventors: Miura; Hideo (Koshigaya, JP), Ogasawara; Makoto (Akishima, JP), Masuda; Hiroo (Tokyo, JP), Murata; Jun (Kunitachi, JP), Okamoto; Noriaki (Ibaraki-ken, JP)

Assignee: Hitachi, Ltd.

International Classification: H01L 21/762 (20060101); H01L 21/70 (20060101); H01L 27/08 (20060101); H01L 029/00 (); H01L 023/58 ()

Expiration Date: 10/30/2018