Patent Number: 6,310,386

Title: High performance chip/package inductor integration

Abstract: A packaged semiconductor circuit for use in processing digital and RF signals. The packaged semiconductor circuit includes a package structure having a first side that includes a metallization layer. The metallization layer has a first part at about a center of the first side and a second part that surrounds the center. The circuit further includes a semiconductor die that is attached to the package structure at about the first part of the metallization layer. The semiconductor die has an interconnection side including an array of bumps that are configured to make electrical connection to selected ones of a first plurality of metallization traces that are defined in the first part of the metallization layer of the package structure. The circuit also includes a spiral inductor trace that is formed from the metallization layer of the package structure and is defined in the first part of the metallization layer. And, selected ones of the array of bumps are electrically interconnected to a first end of the spiral inductor trace and to a second end of the spiral inductor trace, such that selected ones of the array of bumps electrically interconnect the spiral inductor trace of the package structure to the semiconductor die and to selected ones of the first plurality of metallization traces. Furthermore, spiral inductor that is part of the package structure has a significantly improved quality factor "Q" and self-resonant frequency compared to a die fabricated inductor.

Inventors: Shenoy; Jayarama N. (Santa Clara, CA)

Assignee: Philips Electronics North America Corp.

International Classification: H01L 23/64 (20060101); H01L 23/48 (20060101); H01L 23/50 (20060101); H01L 23/58 (20060101); H01L 029/00 ()

Expiration Date: 10/30/2018