Patent Number: 6,310,388

Title: Semiconductor die assembly having leadframe decoupling characters

Abstract: A packaged integrated circuit device with a multi-level leadframe has aplurality of integral capacitors formed by placing a thin dielectric layerbetween a lower leadframe and an upper leadframe, one of the leadframesbeing subdivided into a plurality of portions, each subdivided portionwith an accessible tab for wire attachment. The planar capacitors arebonded to the bottom surface of the chip and act as a die support paddle.Each capacitor may be configured to provide the desired voltage decouplingand noise suppression for a particular portion of the integrated circuitto which it is connected. Capacitors useful for other purposes may belikewise provided in the package.

Inventors: Bissey; Lucien J. (Boise, ID)


International Classification:

Expiration Date: 10/32013