Patent Number: 6,310,397

Title: Butted contact resistance of an SRAM by double VCC implantation

Abstract: Form a butted contact in an SRAM memory device by exposing a contact region on the surface of a doped semiconductor substrate and a conductor stack above a field oxide region on the surface of the substrate. Form an interpolysilicon silicon oxide dielectric layer over the device with an opening framing the contact region and the butt end of the conductor stack near the contact region. Form an undoped upper polysilicon layer on the surface of the SRAM device covering the dielectric layer, the contact region, and the butt end of the conductor stack and then patterned into interconnect and load resistance parts. Form a Vcc mask on the surface of the undoped upper polysilicon layer with a window framing the dielectric layer, the contact region, and the butt end of the conductor stack, leaving an exposed region of the undoped upper polysilicon layer. Ion implant a first dose of Vcc dopant through the window into the undoped upper polysilicon layer at a first energy level, and then ion implant a second dose of Vcc dopant through the window into the buried contact region and the butt end of the conductor stack layer at a higher energy level than the first energy level.

Inventors: Chang; Yeong-Kong (Hsin-Chu, TW), Liao; Hung-Che (Hsin-Chu, TW)

Assignee: Taiwan Semiconductor Manufacturing Company

International Classification: H01L 21/70 (20060101); H01L 27/11 (20060101); H01L 21/8244 (20060101); H01L 023/48 ()

Expiration Date: 10/30/2018